Memory systems are known in the art and used in nearly all microprocessor and digital equipment applications. Memory systems generally utilize different types of memory for different applications. One such type of memory is Static Random Access Memory (“SRAM”). SRAM systems have the advantage of high speed and ease of use as compared to some other types of memory systems. In addition, SRAM systems using MOS technology exhibit extremely low standby power and do not require a refresh cycle to maintain the information stored in the SRAM system. These attributes make SRAM systems particularly desirable for portable equipment, such as laptop computers. As a result, SRAM arrays are becoming an increasingly large portion of many integrated circuits.
In an integrated circuit, SRAM systems are often organized into arrays of memory cells, arranged in rows and columns. Generally, memory cells are set to one of two data states when storing a bit of information. Each memory cell may be referenced by a unique memory address, which includes a row address and a column address. The term “wordline” generally refers to one or more conductors that correspond to a row of memory cells, whereas the term “bitlines” generally refers to a set of conductors that correspond to a column of memory cells. A memory cell typically includes of pair of complementary ports, with each port connected to one of the two bitlines dedicated to that column. Memory devices commonly operate in a read mode and a write mode. When writing to a memory cell, the wordline is activated, thereby activating the entire row in the array of memory cells. A differential voltage is applied to the bitlines between the two complementary input/output ports of the memory cell. The memory cell is latched to a specific logic state with a logic high indicated on one port and a logic low indicated on the other port. When reading from a memory cell, the wordline is activated and the logic states on the bitlines associated with the memory cell is differentially sensed using a sense amplifier. The sense amplifier outputs an amplified signal corresponding to the logic state written to the memory cell.
The easiest way to lower the power consumption of a SRAM memory array is to lower its operational voltages. One common scheme of reducing power consumption is the introduction of a sleep, or power-down, mode in which data is retained. Generally, in sleep mode, data presented in the memory cells is retained in its current state and, to the greatest extent possible, surrounding circuitry is powered down. Depending on the SRAM design, and the particular semiconductor fabrication technology used, the extent to which power down has been possible has varied greatly. Often, circuitry surrounding a given row (i.e., the row-periphery circuitry) cannot be fully, or even partially, powered down. If this row-periphery circuitry is powered down, the stability and integrity of the data stored in a corresponding row is adversely affected.
Furthermore, considerable efforts have been made to reduce the geometry and feature sizes, and thus the operating voltages and power consumption, of almost all semiconductor fabrication technologies. Transistors and other structures fabricated in smaller device technologies generally become more susceptible to leakage current problems. Thus, the movement to smaller device technologies has increased, particularly in SRAM designs, the prevalence and importance of leakage current considerations and problems.
Consider now an SRAM array fabricated in reduced size technology. Minimizing SRAM standby power during sleep mode is critical to many low-power applications (e.g., wireless communications devices). Again, to the greatest extent possible, voltage levels throughout the array are significantly reduced. Logic circuitry is powered off, and array retention voltages are minimized. As a result, leakage currents for most SRAM array circuits in sleep mode are greatly reduced. Where, however, row-periphery circuitry is not, or cannot, be powered down, leakage currents through the row-periphery become, relative to leakage currents of surrounding array circuitry, extremely large. This reduces the power savings realized during sleep mode. Also, since row access directly controls the SRAM access time (read and write), circuitry added to improve row-periphery power down should be optimized to reduce degradation of performance.
As a result, there is a need for a system for reducing power consumption in memory devices, providing a way to power down row-periphery circuitry without negatively impacting performance, or the stability and reliability of data stored in a corresponding row, in an easy, efficient and cost-effective manner.